These are received over the APB interface as a result of a write to the direct_cmd Register. See Direct Command Register. They initialize the SDRAM. The only valid commands that the memory manager can handle are:

You can traverse the memory manager status FSM by writing to the memc_cmd Register. See Memory Controller Command Register. You can only traverse the status FSM states when the device is idle. For example, the ready state can only be entered from the Config state when all direct commands have been completed. The exception to this is the ACTIVE_PAUSE command. You can issue this command when the device is active. When you issue the command, any memory accesses that have not been arbitrated remain in the arbiter until the FSM receives a GO command.

The refresh FSM can issue commands to the arbiter to refresh the SDRAM chips. The refresh counter is clocked by the memory clock to enable the frequency of the device to be scaled without affecting the refresh rate. The refresh rate period is programmable using the RefreshPrd Register. See Refresh Period Register. The value of this register is the count value in mclk cycles.