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This section describes:
Formatting is as follows:
Using the programmed values in the chip_<n>_cfg Registers, see chip_<n>_cfg Registers, that Chapter 3 Programmer’s Model defines, an incoming address has the most significant eight address bits compared with the address match bits using the address mask to ignore any don't care bits to select an external chip.
The transfer is still carried out if there is no match, but the result is undefined.
The row address is determined from the AXI address using bits [5:3] of the memory_cfg Register, and also the brc_n_rbc bit for the selected chip defined in the chip_<n>_cfg Register. See Memory Configuration Register and chip_<n>_cfg Registers.
The column address is determined from the AXI address using bits [2:0] of the memory_cfg Register. See Memory Configuration Register.
The chip bank is determined from the AXI address using bits [5:3] of the memory_cfg2 Register, and also the brc_n_rbc bit for the selected chip defined in the chip_<n>_cfg Register. See memory_cfg2 Register and chip_<n>_cfg Registers.
The number of memory beats is determined, depending on the effective external memory width and the burst size of the AXI access. AXI wrapping bursts are split into two incrementing bursts. AXI fixed bursts are split into AXI burst length memory bursts.
The device only supports a burst length of four on the memory interface.
QoS is defined for the device as a method of increasing the arbitration priority of a read access that requires low-latency read data. The QoS for an AXI read access is determined when it is received by the arbiter. There is no QoS for write accesses.
There are two forms of QoS tracking:
qos_max time-out
qos_min time-out.
The following example shows that the type of QoS, and the QoS value are determined by the id_<n>_cfg Register values pointed to from the ARID bits selected by the qos_master_bits in the memory_cfg Register. See Memory Configuration Register and id_<n>_cfg Registers.
If a transfer is received that has an ARID of 0x5A,
and the qos_master_bits in the memory_cfg Register are set to b010,
then the four ID bits used to match to a QoS pointer are ARID[5:2], giving a value 0x6. See Memory Configuration Register.
This means that when the transfer is received, the id_6_cfg Register determines the qos_enable, qos_min, and qos_max values for this transfer. If the qos_enable bit is HIGH, then the new arbiter entry that is created for this transfer is assigned the qos_min value and qos_max value from the id_6_cfg Register. In addition to this, if the qos_override bit associated with this transfers ID, qos_override[6], is HIGH when the arvalid and arready signals are HIGH, then the qos_min arbiter entry is forced HIGH irrespective of whether the qos_enable bit is HIGH.
The direct command uses the chip select bits [21:20] in the direct_cmd register to select the required memory chip. See Direct Command Register.
The command to be carried out is either:
a self-refresh request from the AXI-C interface
an auto-refresh
a direct command from the APB interface.
It is encoded by the memory manager to match the format that the arbiter requires.
The selection of a command from the AXI interface or the memory manager is fixed, with the memory manager having a higher priority.
The selection between an AXI read access and AXI write access is made using a round-robin arbitration, unless a read access has a low latency QoS value, or if any of the accesses are to a row already open. For more information on arbitration algorithm, see Arbitration algorithm.
See also Formatting from AXI address channels. In this case, it is arbitrated immediately.
For write accesses, no QoS is provided. However, any write access that is a dependency for a QoS read access receives a promoted priority to complete as soon as possible. Dependencies are formed based on the hazard detection logic that Hazard detection describes.
See Formatting from AXI address channels for how the QoS is selected for an AXI read access.
If the QoS enable bit for the ARID is set in the register bank, the QoS maximum latency value is decremented every cycle until it reaches zero.
If the entry is still in the queue when the QoS maximum latency value reaches zero, then the entry becomes high priority. This is called a time-out. Also, any entry in the queue with a minimum latency QoS also produces a time-out. Minimum latency time-outs have priority over maximum latency time-outs.
When an entry times out in this way it forces a time-out onto any entries that it has dependencies against. In normal operation, these entries have already timed out because they have received the same initial QoS value, but been decrementing for longer. The highest priority arbiter entry is serviced next.
One special case exists. This is when or if the qos_override function forces a minimum latency time-out. In this instance, any accesses that the new entry has dependencies against might not have timed out and are forced to time out so that the high-priority entry can start as soon as possible.
A QoS is also provided for the auto-refresh commands from the memory manager. The arbiter keeps track of the number of outstanding auto-refresh commands with a simple increment-decrement counter per chip. If the number of auto-refresh commands reaches a set limit of six, a refresh time-out is signalled. This time-out is sticky, and does not disappear when the number of time-outs drops back below the threshold. Instead, it remains asserted until all of the auto-refreshes have been serviced. This provides a guaranteed refresh rate in the SDRAM.
The following types of hazard exist:
There is a read already in the arbiter queue with the same ID as the incoming entry, that is also a read.
There is a write already in the arbiter queue with the same ID as the incoming entry, that is also a write.
There is a write in the arbiter queue, that has received an early write response, accessing the same location as the incoming read entry.
The arbiter entry is flagged as having a dependency if a hazard is detected. There might be dependencies against a number of other arbiter entries. As the arbiter entries are invalidated, so the dependencies are reduced until finally, there are no outstanding dependencies, and the entry is free to start.
There are no Write-After-Read (WAR) hazard checks in the device. If an AXI master requires ordering between reads and writes to certain memory locations, it must wait for read data before issuing a write to a location it has read from. Similarly, the only RAW hazard checking is that performed when the write response has been issued. If an AXI master required ordering between writes and reads to certain memory locations, it must wait for the write response before issuing the read to the same location.
The scheduler keeps track of the activity of the bank FSMs in the memory interface. This enables the arbiter to select an entry from the queue that does not stall the memory pipeline.
The ordering of commands to be carried out from the arbiter queue is arbitrated with a priority scheme of the following order:
refresh timeouts
minimum latency timeouts
maximum latency timeouts
open-row hits in the same direction
open-row hits in the opposite direction
preparation operations
refreshes.
Preparation operations can be interleaved between memory operations to other banks to improve memory interface utilization.
For every memory burst access necessary to complete an arbiter queue entry, a memory interface command is required.
Command formatting calculates the number of memory interface commands and memory cycles for each command to complete the next arbiter queue entry that is to be sent to the memory interface. It contains an address incrementor and a beat decrementor so that the arbiter entry can be interrupted and restarted.
This keeps track of a configurable number of outstanding exclusive accesses, up to four, as the AMBA AXI Protocol Specification describes. If an exclusive write fails, the data mask for the write is forced LOW, so the data is not written.
When monitoring an exclusive access, the address of any write from another master is compared with the monitored address to check that the location is not being updated.
If the write crosses an address boundary, then all of the least-significant address bits up to that boundary are not compared. Example 2.1 provides information about three transactions.
Example 2.1.
Address = 0x000, size = WORD,
length = 1, ID = 0.
Address = 0x004,
size = WORD, length = 2, ID = 1.
Address
= 0x000, size = WORD, length = 1, ID = 0.
The device marks the exclusive write as having failed because
the write crosses the 0x010 address boundary.
The write, for comparison purposes, has therefore accessed the region 0x000-0x01f because
bits 4:0 have not been compared.
The burst type is always taken to be INCR when calculating
the address region accessed by the write, Therefore, a wrapped transaction
in Example 2.1 that wraps
down to 0x0 rather than cross the boundary, is
treated in the same way. This is the same for a fixed burst that
does not cross the boundary or wrap down to 0x0.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DDI 0418A |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Functional operation > Arbiter |