PrimeCell™ DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 2.2.3. AXI slave interface

2.2.3. AXI slave interface

The AXI programmer’s view is of a flat area of memory. The full range of AXI operations are supported.

The base addresses of the external memory devices are programmable using the chip_cfg Registers. See chip_<n>_cfg Registers.

In addition to reads and writes, exclusive reads and writes are supported in accordance with the AMBA AXI Protocol Specification.

Successful exclusive accesses have an EXOKAY response. All other accesses, including exclusive fail accesses, receive an OKAY response.

Note

The arcache and arprot signals are included in the memory controller port list for completeness only. There is no requirement for the device to use these signals.

This section describes:

Configuration options

You can choose 128-bit, 64-bit, or 32-bit data width.

Write data merging

The device merges interleaved write data to optimize the utilization of the memory interface.

Early BRESP

To enable early write response timing, the device employs write data buffering and issues the BRESP transfer before the data has been committed to the SDRAM. The response is sent after the last data beat is accepted by the AXI interface and stored in the write data buffer. You can disable this feature via the APB feature control register. See feature_ctrl Register.

Note

Exclusive write accesses always wait until the write transaction has been committed to memory before issuing the BRESP transfer.

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