PrimeCell™ DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 2.2.1. Clocking and resets

2.2.1. Clocking and resets

This section describes:

Clocking

The device has the following functional clock inputs:

aclk
mclk
mclkn
mclkx2
mclkx2n
dqs_in_<n> where n is 0<n<bytes of external memory data bus
dqs_in_n_<n> where n is 0<n<bytes of external memory data bus.

These clocks can be grouped into two clock domains:

aclk domain: aclk is in this domain. The aclk domain signals can only be stopped if the external memories are put in self-refresh mode.
mclk domain: All clocks except aclk are in this domain. The mclk signal must be clocked at the rate of the external memory clock speed. The mclk domain signals can only be stopped if the external memories are put in self-refresh mode.

Note

A clock output is provided for every external memory device.

Reset

The device has two reset inputs:

aresetn: This is the reset signal for the aclk domain.
mresetn: This is the reset signal for the mclk domain.

You can change both reset signals asynchronously to their respective clock domain. Internally to the device, the deassertion of the aresetn signal is synchronized to aclk, and the deassertion of the mresetn signal is synchronized to the mclk, mclkn, mclkx2, and mclkx2n clock signals.

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