PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference ManualRevision: r0p1
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3.3.2. Memory Controller Command Register

Writing to the memc_cmd Register enables the programmer’s view FSM to be traversed. If a new command is received to change state, and a previous command to change state has not completed, the pready signal is held LOW until the new command can be carried out.

Figure 3.9 shows the register bit assignments.

Figure 3.9. memc_cmd Register bit assignments

Table 3.3 lists the register bit assignments.

Table 3.3. memc_cmd Register bit assignments

Bits

Name

Function

[31:3]

-

Undefined, write as zero.

[2:0]

memc_cmd

Use the following commands to change the state of the DDR2 DMC:

b000 = Go

b001 = Sleep

b010 = Wakeup

b011 = Pause

b100 = Configure

b111 = Active_Pause.

Note

  • Active_Pause command puts the DDR2 DMC into the Paused state without draining the arbiter queue. This enables you to enter Low-power state to change configuration settings such as memory frequency or timing register values without requiring co-ordination between masters in a multi-master system.

  • If the DDR2 DMC is put into Low-power state after using the Active_Pause command, you must not remove power from it because this results in data loss and violation of the AXI protocol.

  • The DDR2 DMC does not issue refreshes when in the Config state. It is recommended therefore that you use low-power mode to make register updates because this ensures that the memory is put into self-refresh rather than entering the Config state when the memory contains valid data.

  • If you entered the Paused state using the Active_Pause command, you must not attempt to move to the Config state by using the Configure command.

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