PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual A.1. Clock and reset signals

A.1. Clock and reset signals

Table A.1 lists the clock and reset signals.

Table A.1. Clock and reset signals

Signal	Type	Source	Description
mclk	Input	Clock source	Clock for mclk domain.
mclkn	Input	Clock source	Optional^[1] clock for pad interface block.
mclkx2	Input	Clock source	Optional^[1] clock for pad interface block.
mclkx2n	Input	Clock source	Optional^[1] clock for pad interface block.
mresetn	Input	Reset source	Reset for mclk domain. This signal is active LOW.
^[1]These clocks are required if you use the delivered pad interface block.

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