PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 1.1.2. Supported memory widths

1.1.2. Supported memory widths

In each case, the write data FIFO width is equal to the AXI data width. The read data FIFO depth is equal to the greater of the AXI or the effective memory data width.

Table 1.1 lists the supported combinations of memory and AXI bus widths.

Table 1.1. Supported combinations of memory and AXI data widths

Combination	Memory data width	Effective memory data width^[1]	AXI data width
a	16-bit	32-bit	32-bit
b	16-bit	32-bit	64-bit
c	32-bit	64-bit	32-bit
d	32-bit	64-bit	64-bit
e	32-bit	64-bit	128-bit
f	64-bit	128-bit	64-bit
g	64-bit	128-bit	128-bit
^[1]Effective memory data width is equal to the size of transfer on a per-cycle basis on the memory interface.

Note

In addition to the choice of memory data widths at render time, you can modify the DDR2 DMC to use half the configured memory width by either:
- using the memory_width[1:0] tie-off signals
- programming the memory_width field in the memory_cfg2 Register.
When modifying the configured memory width you must ensure that the:
- new memory width is not less than 16 bits
- effective memory width is not less than half the AXI interface data width.

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