PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference ManualRevision: r0p1
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3.3.8. t_mrd Register

The t_mrd Register sets the mode register command time in memory clock cycles. It can only be read from and written to in the Config or Low-power state. Figure 3.15 shows the register bit assignments.

Figure 3.15. t_mrd Register bit assignments

Table 3.9 lists the register bit assignments.

Table 3.9. t_mrd Register bit assignments

Bits

Name

Function

[31:7]

-

Read undefined, write as zero

[6:0]

t_mrdSets mode register command time in memory clock cycles
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