PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 3.3.1. Memory Controller Status Register

3.3.1. Memory Controller Status Register

The memc_status Register provides information about the configuration of the DDR2 DMC and its current state. It cannot be read in either the Reset or POR states. Figure 3.8 shows the register bit assignments.

Figure 3.8. memc_status Register bit assignments

Table 3.2 lists the register bit assignments.

Table 3.2. memc_status Register bit assignments

Bits	Name	Function
[31:14]	-	Read undefined.
[13:12]	memory_banks	Returns the maximum number of banks per memory chip. This is a rendered option, and is static for a given configuration: b00 = 4 banks b01 = 2 banks, not supported b10 = 1 banks, not supported b11 = 8 banks.
[11:10]	exclusive_monitors	Returns the number of exclusive access monitor resources implemented in the DDR2 DMC: b00 = 0 monitors b01 = 1 monitor b10 = 2 monitors b11 = 4 monitors.
[9]	-	Undefined, read as zero.
[8:7]	memory_chips	Returns the number of different chip selects that the DDR2 DMC supports: b00 = 1 chip b01 = 2 chips b10 = 3 chips b11 = 4 chips.
[6:4]	memory_type	Returns the type of SDRAM that the DDR2 DMC supports: b000-b100 = reserved b101 = DDR2 SDRAM b110-b111 = reserved.
[3:2]	memory_width	Returns the physical width of the external memory: b00 = 16-bit b01 = 32-bit b10 = 64-bit b11 = 128-bit.
[1:0]	memc_status	Returns the state of the memory controller: b00 = Config b01 = Ready b10 = Paused b11 = Low-power.

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