PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference ManualRevision: r0p1
Home > Programmers Model > Register descriptions > Refresh Period Register

3.3.5. Refresh Period Register

The refresh_prd Register sets the memory refresh period. It can only be read from and written to in the Config or Low-power state. Figure 3.12 shows the register bit assignments.

Figure 3.12. refresh_prd Register bit assignments

Table 3.6 lists the register bit assignments.

Table 3.6. refresh_prd Register bit assignments

Bits

Name

Function

[31:15]

-

Read undefined, write as zero

[14:0]

refresh_prdMemory refresh period in memory clock cycles
Copyright © 2007 ARM Limited. All rights reserved.ARM DDI 0418C
Non-Confidential
PDF file icon  PDF version
Home > Programmers Model > Register descriptions > Refresh Period Register