PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 2.1.3. Memory manager

2.1.3. Memory manager

The memory manager tracks and controls the current state of the DDR2 DMC using a Finite State Machine (FSM). See Figure 2.3.

Figure 2.3. clk domain state diagram

In Figure 2.3, non-state moving transitions are omitted for clarity. See Table 2.2 for valid system states.

Note

If you move into the Pause state using Active_Pause, you are not permitted to enter the Config state.
For the two cycles following POR, do not consider the DDR2 DMC to be in the Config state. For this reason, register access restrictions apply.
You can only use the AXI low-power interface to move in and out of the Low-power state from the Ready state.
If you enter the Low-power state using the APB interface, you must also exit the Low-power state using the APB interface.
If you enter the Low-power state using the AXI low-power interface, you must also exit the Low-power state using the AXI low-power interface.
Autorefresh commands are only issued to the memory when in the Ready state.

APB commands to the Direct Command Register, see Direct Command Register, or the AXI low-power interface, control the state of the device. Figure 2.4 shows AXI low-power interface channel signals.

Figure 2.4. AXI low-power interface channel signals

The AXI low-power interface channel enables low-power mode to be entered using discrete lines. You can tie-off this interface to be inactive if it is not required.

The APB slave interface stalls the psel and penable signals using the pready signal if a previous command has not completed.

If an APB command is received that is illegal to carry out from the current state, then it is ignored and the FSM stays in the current state.

The memory manager enables the APB slave interface to directly send initialization commands to the external DDR2 SDRAM and periodically generate refresh commands for the external DDR2 SDRAM. This is done using the direct_cmd register. See the following sections for more information on this register:

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