The pad interface is a replaceable block designed to operate
with DDR2 SDRAM memory. It provides a flip-flop for each external
signal.
Figure 2.7 shows
the pad interface external connections.
Pad interface to external memory devices
The pad interface block registers the relevant command signals
with clocks that enable the external memory device timing to be
met.
It is expected that a Delay-Locked Loop (DLL)
is required to delay the dqs_in_<n> and dqs_in_n_<n> signals coming back
from the memories with respect to the dq_in[MEMWIDTH-1:0] data
bus. The standard delay for the dqs_in_<n> and dqs_in_n_<n> signals is a quarter
clock period of mclk. The DLL
is not included in the DDR2 DMC. The asetbok signal
enables DLLs to update at safe points in time. See Table A.2.
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