PrimeCell ® DDR2Dynamic Memory Controller (PL341) Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on this DDR2 DMC
Feedback on this manual
1. Introduction
1.1. About the PrimeCell DDR2 DMC (PL341)
1.1.1. Features of the DDR2 DMC
1.1.2. Supported memory widths
1.1.3. AXI interface attributes
1.2. Supported memory devices
1.3. Product revisions
2. Functional Overview
2.1. Functional description
2.1.1. AXI slave interface
2.1.2. Arbiter
2.1.3. Memory manager
2.1.4. APB slave interface
2.1.5. Memory interface
2.1.6. Pad interface
2.2. Functional operation
2.2.1. Clocking and resets
2.2.2. Miscellaneous signals
2.2.3. AXI slave interface
2.2.4. Arbiter
2.2.5. Memory manager
2.2.6. APB slave interface
2.2.7. Memory interface
2.2.8. Pad interface
2.2.9. Initialization
2.2.10. Power-down support and usage model
3. Programmers Model
3.1. About the programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Controller Command Register
3.3.3. Direct Command Register
3.3.4. Memory Configuration Register
3.3.5. Refresh Period Register
3.3.6. CAS Latency Register
3.3.7. Write Latency Register
3.3.8. t_mrd Register
3.3.9. t_ras Register
3.3.10. t_rc Register
3.3.11. t_rcd Register
3.3.12. t_rfc Register
3.3.13. t_rp Register
3.3.14. t_rrd Register
3.3.15. t_wr Register
3.3.16. t_wtr Register
3.3.17. t_xp Register
3.3.18. t_xsr Register
3.3.19. t_esr Register
3.3.20. memory_cfg2 Register
3.3.21. memory_cfg3 Register
3.3.22. t_faw Register
3.3.23. id_<n>_cfg Registers
3.3.24. chip_<n>_cfg Registers
3.3.25. user_status Register
3.3.26. user_config0 Register
3.3.27. user_config1 Register
3.3.28. feature_ctrl Register
3.3.29. Peripheral Identification Registers0-3
3.3.30. PrimeCell Identification Registers 0-3
4. Programmers Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration OutputsRegister
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. Pad interface signals
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Example system
2.1. Block diagram
2.2. AXI slave interface connections
2.3. clk domain state diagram
2.4. AXI low-power interface channel signals
2.5. APB interface
2.6. mclk domain state diagram
2.7. Pad interface external connections
2.8. Command control output timing
2.9. Activate to read or write commandtiming, tRCD
2.10. Four activate window command timing,tFAW
2.11. Bank activate to bank activate orAutorefresh command timing, tRC
2.12. Bank activate to different bank activatefor a memory timing, tRRD
2.13. Precharge to command and auto-refreshtiming, tRP and tRFC
2.14. Activate to precharge, and prechargeto precharge timing, tRAS and tRP
2.15. Mode register write to command timing,tMRD
2.16. Self-refresh entry and exit timing,tESR and tXSR
2.17. Power down entry and exit timing,tXP
2.18. Data output timing, tWTR
2.19. Data output timing, write latency= 2
2.20. Data input timing
2.21. System state transitions
3.1. Register map
3.2. Configuration register map
3.3. AXI ID configuration register map
3.4. Chip configuration registers map
3.5. User configuration memory map
3.6. Integration test register map
3.7. Identification register map
3.8. memc_status Register bit assignments
3.9. memc_cmd Register bit assignments
3.10. direct_cmd Register bit assignments
3.11. memory_cfg Register bit assignments
3.12. refresh_prd Register bit assignments
3.13. cas_latency Register bit assignments
3.14. write_latency Register bit assignments
3.15. t_mrd Register bit assignments
3.16. t_ras Register bit assignments
3.17. t_rc Register bit assignments
3.18. t_rcd Register bit assignments
3.19. t_rfc Register bit assignments
3.20. t_rp Register bit assignments
3.21. t_rrd Register bit assignments
3.22. t_wr Register bit assignments
3.23. t_wtr Register bit assignments
3.24. t_xp Register bit assignments
3.25. t_xsr Register bit assignments
3.26. t_esr Register bit assignments
3.27. memory_cfg2 Register bit assignments
3.28. memory_cfg3 Register bit assignments
3.29. t_faw Register bit assignments
3.30. id_<n>_cfg Registers bit assignments
3.31. chip_<n>_cfg Registers bit assignments
3.32. feature_ctrl Register bit assignments
3.33. periph_id Register bit assignments
3.34. pcell_id Register bit assignments
4.1. Integration test register map
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments

List of Tables

1.1. Supported combinations of memory and AXI data widths
1.2. Attribute formats
2.1. Example DDR2 setup
2.2. Valid system states for FSMs
2.3. Recommended power states
3.1. DDR2 DMC register summary
3.2. memc_status Register bit assignments
3.3. memc_cmd Register bit assignments
3.4. direct_cmd Register bit assignments
3.5. memory_cfg Register bit assignments
3.6. refresh_prd Register bit assignments
3.7. cas_latency Register bit assignments
3.8. write_latency Register bit assignments
3.9. t_mrd Register bit assignments
3.10. t_ras Register bit assignments
3.11. t_rc Register bit assignments
3.12. t_rcd Register bit assignments
3.13. t_rfc Register bit assignments
3.14. t_rp Register bit assignments
3.15. t_rrd Register bit assignments
3.16. t_wr Register bit assignments
3.17. t_wtr Register bit assignments
3.18. t_xp Register bit assignments
3.19. t_xsr Register bit assignments
3.20. t_esr Register bit assignments
3.21. memory_cfg2 Register bit assignments
3.22. memory_cfg3 Register bit assignments
3.23. t_faw Register bit assignments
3.24. id_<n>_cfg Registers bit assignments
3.25. chip_<n>_cfg Registers bit assignments
3.26. user_status Registers bit assignments
3.27. user_config0 Registers bit assignments
3.28. user_config1 Registers bit assignments
3.29. feature_ctrl Registers bit assignments
3.30. periph_id Register bit assignments
3.31. periph_id_0 Register bit assignments
3.32. periph_id_1 Register bit assignments
3.33. periph_id_2 Register bit assignments
3.34. periph_id_3 Register bit assignments
3.35. pcell_id Register bit assignments
4.1. DDR2 DMC test register summary
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. Pad interface signals

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited, except as otherwise stated below in this proprietarynotice. Other brands and names mentioned herein may be the trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 29March 2007 First release for r0p0
Revision B 16October 2007 First release for r0p1
Revision C 19December 2007 Update for r0p1
Copyright © 2007 ARM Limited. All rights reserved. ARM DDI 0418C
Non-Confidential