PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual: 1.2. Product revisions

1.2. Product revisions

This section describes the differences in functionality between product revisions of the DDR2 DMC:

r0p0-r0p1

Contains the following differences in functionality:

the revision field in the periph_id_2 Register returns 0x1 or 0x2, see Peripheral Identification Register 2.

r0p1 - r1p0

This release includes:

the option to configure the DDR2 DMC to support:
- a DFI pad interface, see Pad interface
- ECC, see ECC block
the controller can enter the Config state from the Paused state, irrespective of which command moved the controller to the Paused state, see Memory manager
supports memory bursts of four and eight, see Formatting from AXI address channels
configurable bus width for the user_status, user_config0, and user_config1 signals, see User signals
the revision field in the periph_id_2 Register returns 0x3, see Peripheral Identification Register 2.

Copyright © 2007, 2009 ARM Limited. All rights reserved.	ARM DDI 0418D
Non-Confidential
PDF version