PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference ManualRevision: r1p0
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3.3.7. Write Latency Register

The write_latency Register characteristics are:

Purpose

Returns the write latency in memory clock cycles.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.14 shows the write_latency Register bit assignments.

Figure 3.14. write_latency Register bit assignments


Table 3.8 shows the write_latency Register bit assignments.

Table 3.8. write_latency Register bit assignments

BitsNameFunction
[31:3]-Read undefined.

[2:0]

write_latency

Returns the write latency in memory clock cycles. Supported values are 2-5.

Note

write_latency = cas_latency – 1.


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