PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual: 4.1.3. Integration Outputs Register

The int_outputs Register characteristics are:

Purpose

Enables an external master to control the state of the following outputs:

Usage constraints

Only accessible in Config state.
Some bits are only present when a DDR2 DMC supports Error Correction Code (ECC).
Integration test logic must be enabled otherwise it ignores writes and reads return 0x0. To enable the integration test logic see Integration Configuration Register.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 4.1.

Figure 4.4 shows the int_outputs Register bit assignments.

Figure 4.4. int_outputs Register bit assignments

Table 4.4 shows the int_outputs Register bit assignments.

Table 4.4. int_outputs Register bit assignments

Bits	Name	Function
[31:5]	-	Write as zero
[4]	ecc_overflow_int	Controls the state of the ecc_overflow_int output if the DDR2 DMC supports ECC
[3]	ecc_ded_int	Controls the state of the ecc_ded_int output if the DDR2 DMC supports ECC
[2]	ecc_sec_int	Controls the state of the ecc_sec_int output if the DDR2 DMC supports ECC
[1]	csysack_int	Controls the state of the csysack output
[0]	cactive_int	Controls the state of the cactive output

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