Figure 2.12 shows a block diagram of the DDR2 DMC.
Figure 2.12. Block diagram
This section describes:
Clocking and resets
AXI slave interface
AXI low-power interface
APB slave interface
Tie-off signals
Miscellaneous signals
Arbiter
Memory manager
ECC block
Memory interface
Pad interface
Initialization
Power-down support and usage model.