PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference ManualRevision: r1p0
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3.1.1. Register map

The register map of the DDR2 DMC spans a 4KB region, see Figure 3.1.

Figure 3.1. Register map


In Figure 3.1 the register map consists of the following main blocks:

DDR2 DMC configuration

Figure 3.2 shows the DDR2 DMC configuration register map.

Figure 3.2. Configuration register map


QoS registers

Figure 3.3 shows the QoS register map.

Figure 3.3. QoS register map


Chip configuration

Figure 3.4 shows the chip configuration register map.

Figure 3.4. Chip configuration register map


User registers

Figure 3.5 shows the memory map for the Feature Control Register and the following user signals:

  • user_config1[ ]

  • user_config0[ ]

  • user_status[ ].

Figure 3.5. User register map


ECC registers

Figure 3.6 shows the Error Correction Code (ECC) memory map.

Figure 3.6. ECC configuration memory map


Integration test

Use these registers to verify correct integration of the DDR2 DMC within a system, by enabling non-AMBA signals to be set and read.

Component configuration

Figure 3.7 shows the PrimeCell identification register map.

Figure 3.7. Component configuration register map


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