PrimeCell® DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual

Revision: r1p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the PrimeCell DDR2 DMC (PL341)
1.1.1. Features of the DDR2 DMC
1.1.2. Supported memory widths
1.1.3. Supported memory devices
1.2. Product revisions
2. Functional Description
2.1. Functional overview
2.1.1. AXI slave interface
2.1.2. AXI low-power interface
2.1.3. APB slave interface
2.1.4. Tie-off signals
2.1.5. User signals
2.1.6. Interrupt signals
2.1.7. Memory interface
2.1.8. Pad interface
2.1.9. QoS signal
2.2. Functional operation
2.2.1. Clocking and resets
2.2.2. AXI slave interface
2.2.3. AXI low-power interface
2.2.4. APB slave interface
2.2.5. Tie-off signals
2.2.6. Miscellaneous signals
2.2.7. Arbiter
2.2.8. Memory manager
2.2.9. ECC block
2.2.10. Memory interface
2.2.11. Pad interface
2.2.12. Initialization
2.2.13. Power-down support and usage model
3. Programmers Model
3.1. About the programmers model
3.1.1. Register map
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Controller Command Register
3.3.3. Direct Command Register
3.3.4. Memory Configuration Register
3.3.5. Refresh Period Register
3.3.6. CAS Latency Register
3.3.7. Write Latency Register
3.3.8. MODEREG to Command Timing Register
3.3.9. ACTIVE to PRECHARGE Timing Register
3.3.10. ACTIVE to ACTIVE Timing Register
3.3.11. ACTIVE to Read or Write Timing Register
3.3.12. AUTO REFRESH to Command Timing Register
3.3.13. PRECHARGE to Command Timing Register
3.3.14. ACTIVE to ACTIVE Different Bank Timing Register
3.3.15. Write to PRECHARGE Timing Register
3.3.16. Write to Read Timing Register
3.3.17. Exit Power-down Timing Register
3.3.18. Exit Self-refresh Timing Register
3.3.19. Self-refresh to Command Timing Register
3.3.20. Memory Configuration 2 Register
3.3.21. Memory Configuration 3 Register
3.3.22. Four Activate Window Timing Register
3.3.23. Update Type Register
3.3.24. Read Data Enable Timing Register
3.3.25. Write Data Enable Timing Register
3.3.26. QoS Configuration Registers
3.3.27. Chip Configuration Registers
3.3.28. User Status Register
3.3.29. User Config 0 Register
3.3.30. User Config 1 Register
3.3.31. Feature Control Register
3.3.32. ECC Control Register
3.3.33. ECC Interrupt Clear Register
3.3.34. ECC Status Register
3.3.35. ECC Information Register
3.3.36. Peripheral Identification Registers
3.3.37. PrimeCell Identification Registers
4. Programmers Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration Outputs Register
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.2.1. QoS
A.2.2. Tie-offs
A.2.3. asetbok signal
A.2.4. User signals
A.2.5. Interrupt signals
A.2.6. Scan test
A.3. AXI signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.3.6. AXI low-power interface signals
A.4. APB signals
A.5. Pad interface signals
A.5.1. Legacy pad interface
A.5.2. DFI pad interface
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example system
2.1. DDR2 DMC interfaces
2.2. AXI slave interface signals
2.3. AXI low-power interface channel signals
2.4. APB interface
2.5. Tie-off signals
2.6. User signals
2.7. Interrupt signals
2.8. mclk domain state diagram
2.9. Legacy pad interface signals
2.10. DFI pad interface signals
2.11. QoS signal
2.12. Block diagram
2.13. aclk domain state diagram
2.14. Command control output timing
2.15. ACTIVE command to Read or Write command timing, tRCD
2.16. Four activate window command timing, tFAW
2.17. Same bank ACTIVE to ACTIVE, and ACTIVE to AUTO REFRESH command timing, tRC
2.18. Different bank ACTIVE to ACTIVE command timing, tRRD
2.19. PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC
2.21. MODEREG to command timing, tMRD
2.22. Self-refresh entry and exit timing, tESR and tXSR
2.23. Power down entry and exit timing, tXP
2.24. Data output timing, tWTR
2.25. Data output timing, write latency = 2
2.26. Data input timing
2.27. System state transitions
3.1. Register map
3.2. Configuration register map
3.3. QoS register map
3.4. Chip configuration register map
3.5. User register map
3.6. ECC configuration memory map
3.7. Component configuration register map
3.8. memc_status Register bit assignments
3.9. memc_cmd Register bit assignments
3.10. direct_cmd Register bit assignments
3.11. memory_cfg Register bit assignments
3.12. refresh_prd Register bit assignments
3.13. cas_latency Register bit assignments
3.14. write_latency Register bit assignments
3.15. t_mrd Register bit assignments
3.16. t_ras Register bit assignments
3.17. t_rc Register bit assignments
3.18. t_rcd Register bit assignments
3.19. t_rfc Register bit assignments
3.20. t_rp Register bit assignments
3.21. t_rrd Register bit assignments
3.22. t_wr Register bit assignments
3.23. t_wtr Register bit assignments
3.24. t_xp Register bit assignments
3.25. t_xsr Register bit assignments
3.26. t_esr Register bit assignments
3.27. memory_cfg2 Register bit assignments
3.28. memory_cfg3 Register bit assignments
3.29. t_faw Register bit assignments
3.30. update_type Register bit assignments
3.31. t_rddata_en Register bit assignments
3.32. t_wrlat_diff Register bit assignments
3.33. id_<n>_cfg Registers bit assignments
3.34. chip_cfg<n> Registers bit assignments
3.35. user_status Register bit assignments
3.36. user_config0 Register bit assignments
3.37. user_config1 Register bit assignments
3.38. feature_ctrl Register bit assignments
3.39. ecc_control Register bit assignments
3.40. ecc_int_clr Register bit assignments
3.41. ecc_status Register bit assignments
3.42. ecc_info0 Register bit assignments
3.43. periph_id_[3:0] Register bit assignments
3.44. pcell_id Register bit assignments
4.1. Integration test register map
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments

List of Tables

1.1. Supported combinations of memory and AXI data widths
2.1. AXI slave interface attributes
2.2. Controller initialization example
2.3. DDR2 device initialization
2.4. Valid system states for FSMs
2.5. Recommended power states
3.1. DDR2 DMC register summary
3.2. memc_status Register bit assignments
3.3. memc_cmd Register bit assignments
3.4. direct_cmd Register bit assignments
3.5. memory_cfg Register bit assignments
3.6. refresh_prd Register bit assignments
3.7. cas_latency Register bit assignments
3.8. write_latency Register bit assignments
3.9. t_mrd Register bit assignments
3.10. t_ras Register bit assignments
3.11. t_rc Register bit assignments
3.12. t_rcd Register bit assignments
3.13. t_rfc Register bit assignments
3.14. t_rp Register bit assignments
3.15. t_rrd Register bit assignments
3.16. t_wr Register bit assignments
3.17. t_wtr Register bit assignments
3.18. t_xp Register bit assignments
3.19. t_xsr Register bit assignments
3.20. t_esr Register bit assignments
3.21. memory_cfg2 Register bit assignments
3.22. memory_cfg3 Register bit assignments
3.23. t_faw Register bit assignments
3.24. update_type Register bit assignments
3.25. t_rddata_en Register bit assignments
3.26. t_wrlat_diff Register bit assignments
3.27. id_<n>_cfg Registers bit assignments
3.28. chip_cfg<n> Registers bit assignments
3.29. user_status Register bit assignments
3.30. user_config0 Register bit assignments
3.31. user_config1 Register bit assignments
3.32. feature_ctrl Registers bit assignments
3.33. ecc_control Registers bit assignments
3.34. ecc_int_clr Registers bit assignments
3.35. ecc_status Registers bit assignments
3.36. ecc_info0 Registers bit assignments
3.37. Conceptual peripheral ID register bit assignments
3.38. periph_id_0 Register bit assignments
3.39. periph_id_1 Register bit assignments
3.40. periph_id_2 Register bit assignments
3.41. periph_id_3 Register bit assignments
3.42. pcell_id Register bit assignments
4.1. DDR2 DMC test register summary
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. Clock and reset signals
A.2. QoS signal
A.3. Tie-off signals
A.4. asetbok signal
A.5. User signals
A.6. ECC interrupt signals
A.7. Scan test signals
A.8. Write address channel signals
A.9. Write data channel signals
A.10. Write response channel signals
A.11. Read address channel signals
A.12. Read data channel signals
A.13. AXI low-power interface signals
A.14. APB interface signals
A.15. Legacy pad interface signals
A.16. DFI pad interface signals
B.1. Differences between issue C and issue D

Proprietary Notice

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A29 March 2007First release for r0p0
Revision B16 October 2007First release for r0p1
Revision C19 December 2007Update for r0p1
Revision D17 April 2009First release for r1p0
Copyright © 2007, 2009 ARM Limited. All rights reserved.ARM DDI 0418D