4.1. Integration test registers

Test registers are provided for integration testing.

Figure 4.1 shows the integration test register map.

Figure 4.1. Integration test register map

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.1 shows the integration test registers in base offset order.

Table 4.1. DDR2 DMC test register summary

OffsetNameTypeResetDescription
0xE00int_cfgRW0x0Integration Configuration Register
0xE04int_inputsRO- [a]Integration Inputs Register
0xE08int_outputsWO-Integration Outputs Register

[a] Dependent on the state of various input signals.


Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910