2.2.9. ECC block

The DDR2 DMC can be configured to include ECC support.

The ECC mechanism uses a Hamming code variant, using 1-bit correction 2-bit detection. Program the ecc_control Register to enable the controller to use the ECC block. See ECC Control Register.

When ECC is enabled, the controller requires writes:

If these conditions are violated then the controller writes invalid ECC data.

When the controller performs a READ command, if it detects:

Note

The controller can only assert ecc_sec_int or ecc_ded_int when the corresponding interrupt enable bit is set in the ecc_control Register. See ECC Information Register.

If the controller is signaling a single interrupt then an AMBA master can discover the address location that triggered an interrupt by accessing the ecc_info0 Register. See ECC Information Register.

The controller provides the ecc_overflow_int signal to indicate when an interrupt overflow occurs, that is:

Note

If the controller detects two or more errors within the same aligned AXI-width region of a burst then it does not set the overflow bit and ecc_overflow_int remains LOW. However, it still performs error correction and detection on each memory width portion of the burst.

The controller controls the enabling and disabling of the ecc_overflow_int signal as follows:

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910