3.3.23. Update Type Register

The update_type Register characteristics are:

Purpose

Controls how the DDR2 DMC responds when it receives any of the four possible update type requests from a PHY device.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available when a DDR2 DMC is configured to support a DFI pad interface.

Attributes

See the register summary in Table 3.1.

Figure 3.30 shows the update_type Register bit assignments.

Figure 3.30. update_type Register bit assignments

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Table 3.24 shows the update_type Register bit assignments.

Table 3.24. update_type Register bit assignments

BitsNameFunction
[31:8]-Read undefined, write as zero.
[7:6]update_type3

Controls how the DDR2 DMC responds to a DFI update request type 3, that is, when a PHY sets dfi_phyupd_type[1:0] to 0b11:

0b00 = Put the memory devices in self-refresh mode then stall the DFI.

0b01 = Stall the DFI.

0b10 - 0b11 = Reserved.

[5:4]update_type2

Controls how the DDR2 DMC responds to a DFI update request type 2, that is, when a PHY sets dfi_phyupd_type[1:0] to 0b10:

0b00 = Put the memory devices in self-refresh mode then stall the DFI.

0b01 = Stall the DFI.

0b10 - 0b11 = Reserved.

[3:2]update_type1

Controls how the DDR2 DMC responds to a DFI update request type 1, that is, when a PHY sets dfi_phyupd_type[1:0] to 0b01:

0b00 = Put the memory devices in self-refresh mode then stall the DFI.

0b01 = Stall the DFI.

0b10 - 0b11 = Reserved.

[1:0]update_type0

Controls how the DDR2 DMC responds to a DFI update request type 0, that is, when a PHY sets dfi_phyupd_type[1:0] to 0b00:

0b00 = Put the memory devices in self-refresh mode then stall the DFI.

0b01 = Stall the DFI.

0b10 - 0b11 = Reserved.


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