3.3.34. ECC Status Register

The ecc_status Register characteristics are:

Purpose

Returns the status of the ECC interrupts.

Usage constraints

No usage constraints.

Configurations

Available when a DDR2 DMC is configured to support ECC.

Attributes

See the register summary in Table 3.1.

Figure 3.41 shows the ecc_status Register bit assignments.

Figure 3.41. ecc_status Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.35 shows the ecc_status Register bit assignments.

Table 3.35. ecc_status Registers bit assignments

BitsNameFunction
[31:3]-Undefined.

[2]

ecc_int_overflow

Returns the status of the ECC overflow signal:

0 = ecc_overflow_int is LOW

1 = ecc_overflow_int is HIGH.

[1]

ecc_ded_status

Returns the status of the double-error detect signal:

0 = ecc_ded_int is LOW

1 = ecc_ded_int is HIGH.

[0]

ecc_sec_status

Returns the status of the single-error correct signal:

0 = ecc_sec_int is LOW

1 = ecc_sec_int is HIGH.


Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910