3.3.24. Read Data Enable Timing Register

The t_rddata_en Register characteristics are:


Controls the trddata_en timing parameter for a DFI pad interface.

Usage constraints

Only accessible in Config or Low_power state.


Available when a DDR2 DMC is configured to support a DFI pad interface.


See the register summary in Table 3.1.

Figure 3.31 shows the t_rddata_en Register bit assignments.

Figure 3.31. t_rddata_en Register bit assignments

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Table 3.25 shows the t_rddata_en Register bit assignments.

Table 3.25. t_rddata_en Register bit assignments

[31:4]-Read undefined, write as zero.



After a DDR2 DMC issues a Read command from the DFI pad interface then this field sets the number of mclk cycles before dfi_rddata_en[MEMORY_BYTES-1:0] goes HIGH.

The valid values for this field depend on the cas_latency setting and the limits are:


cas_latency- 2


cas_latency+ 5

For example, if cas_latency = 3 then set this field to any value between 0b0001 and 0b1000. The cas_latency value is set using the CAS Latency Register.

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