CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 3.3.25. Write Data Enable Timing Register

The t_wrlat_diff Register characteristics are:

Purpose

Controls the t_{phy_wrlat} timing parameter for a DFI pad interface to be either:

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available when a DDR2 DMC is configured to support a DFI pad interface.

Attributes

See the register summary in Table 3.1.

Figure 3.32 shows the t_wrlat_diff Register bit assignments.

Figure 3.32. t_wrlat_diff Register bit assignments

Table 3.26 shows the t_wrlat_diff Register bit assignments.

Table 3.26. t_wrlat_diff Register bit assignments

Bits	Name	Function
[31:1]	-	Read undefined, write as zero.
[0]	t_wrlat_diff	Controls the timing relationship between t_{phy_wrlat} and write_latency to be either: 0 = t_{phy_wrlat} is write_latency - 1. This is the default. 1 = t_{phy_wrlat} is write_latency - 2. The write_latency value is set using the Write Latency Register.

Bits

Name

Function

[31:1]

Read undefined, write as zero.

[0]

t_wrlat_diff

Controls the timing relationship between t_{phy_wrlat} and write_latency to be either:

0 = t_{phy_wrlat} is write_latency - 1. This is the default.

1 = t_{phy_wrlat} is write_latency - 2.

The write_latency value is set using the Write Latency Register.

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