3.3.25. Write Data Enable Timing Register

The t_wrlat_diff Register characteristics are:

Purpose

Controls the tphy_wrlat timing parameter for a DFI pad interface to be either:

  • write_latency - 1

  • write_latency - 2.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available when a DDR2 DMC is configured to support a DFI pad interface.

Attributes

See the register summary in Table 3.1.

Figure 3.32 shows the t_wrlat_diff Register bit assignments.

Figure 3.32. t_wrlat_diff Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.26 shows the t_wrlat_diff Register bit assignments.

Table 3.26. t_wrlat_diff Register bit assignments

BitsNameFunction
[31:1]-Read undefined, write as zero.

[0]

t_wrlat_diff

Controls the timing relationship between tphy_wrlat and write_latency to be either:

0 = tphy_wrlat is write_latency - 1. This is the default.

1 = tphy_wrlat is write_latency - 2.

The write_latency value is set using the Write Latency Register.


Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910