CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.33. ECC Interrupt Clear Register

The ecc_int_clr Register characteristics are:

Purpose

Controls the clearing of interrupts.

Usage constraints

No usage constraints.

Configurations

Available when a DDR2 DMC is configured to support ECC.

Attributes

See the register summary in Table 3.1.

Figure 3.40 shows the ecc_int_clr Register bit assignments.

Figure 3.40. ecc_int_clr Register bit assignments

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Table 3.34 shows the ecc_int_clr Register bit assignments.

Table 3.34. ecc_int_clr Registers bit assignments

BitsNameFunction
[31:3]-Undefined, write as zero.
[2]ecc_overflow_clr

Controls the clearing of the ECC overflow signal. Write:

0 = state of ecc_overflow_int is unchanged

1 = DDR2 DMC sets ecc_overflow_int LOW.

[1]ecc_ded_int_clr

Controls the clearing of the ECC double-error detect signal. Write:

0 = state of ecc_ded_int is unchanged

1 = DDR2 DMC sets ecc_ded_int LOW.

[0]ecc_sec_int_clr

Controls the clearing of the ECC single-error correct signal. Write:

0 = state of ecc_sec_int is unchanged

1 = DDR2 DMC sets ecc_sec_int LOW.


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