3.3.32. ECC Control Register

The ecc_control Register characteristics are:

Purpose

Controls the:

  • enabling of the single-error correct, double-error detect (SECDED) behavior

  • enabling of interrupts.

Usage constraints

No usage constraints.

Configurations

Available when a DDR2 DMC is configured to support ECC.

Attributes

See the register summary in Table 3.1.

Figure 3.39 shows the ecc_control Register bit assignments.

Figure 3.39. ecc_control Register bit assignments

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Table 3.33 shows the ecc_control Register bit assignments.

Table 3.33. ecc_control Registers bit assignments

BitsNameFunction
[31:3]-Undefined, write as zero.
[2]ecc_ded_int_en

Controls the enabling of the double-error detect interrupt:

0 = disabled, the DDR2 DMC sets ecc_ded_int LOW. This is the default.

1 = enabled, the ECC block can modify the state of ecc_ded_int.

[1]ecc_sec_int_en

Controls the clearing of the ECC single-error correct signal. Write:

0 = disabled, the DDR2 DMC sets ecc_sec_int LOW. This is the default.

1 = enabled, the ECC block can modify the state of ecc_sec_int.

[0]ecc_enable

Controls the enabling of the SECDED ECC behavior:

0 = disabled

1 = enabled.


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