Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Differences between issue C and issue D

Added requirement to issue an AUTO REFRESH command before the DDR2 DMC moves from the Config state to the Paused stateMemory managerAll revisions
Updated the clock_cfg field descriptionTable 3.21All revisions

Updated the write data value for the following registers:

  • t_xsr

  • t_esr

  • memory_cfg2

Table 2.3

All revisions

Updated the memory device initialization exampleDDR2 device initializationAll revisions
Updated the reset value of the memory_cfg Register from 0x00010020 to 0x00010021Table 3.1r1p0

Updated the reset value of the following registers:

  • t_rfc Register from 0x00002123 to 0x00002023

  • t_rcd and t_rp Registers from 0x00000305 to 0x00000205

  • t_faw Register from 0x00000011 to 0x00001114

All revisions

Updated the reset value of the refresh_prd Register from 0x00000A2C to 0x000001E7r0p1
Added conditions about changing the power_dwn_prd bitMemory Configuration RegisterAll revisions
Updated the function of the row_bits field when set to 0b000 or 0b001
Updated the supported values for the cas_latency field from 2-6 to 3-6CAS Latency RegisterAll revisions
Increased the bit widths for the schedule_rfc and rfc fieldsAUTO REFRESH to Command Timing Registerr1p0
Added usage constraints for writesExit Power-down Timing RegisterAll revisions
Changed memory_width field to memory_width2Memory Configuration 2 RegisterAll revisions

Updated the most significant byte of the conceptual peripheral ID register

All revisions

Added requirement to set cactive and csysack HIGH when the controller exits integration test modeIntegration Configuration RegisterAll revisions
Added an _int suffix to the cactive and csysack bitsIntegration Outputs RegisterAll revisions
Added configurable bus width for the user_status, user_config0, and user_config1 signalsThroughout bookr1p0

Table B.2. Differences between issue D and issue E

Updated information on exclusive access monitorExclusive accessAll revisions
Added 0x4 to the revision fieldPeripheral Identification Register 2r1p1
Updated description of the memc_status fieldMemory Controller Status Registerr1px

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