| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
 PDF version | |
| Home > Signal Descriptions > AXI signals > Read address channel signals |
| |||
| Home > Signal Descriptions > AXI signals > Read address channel signals | |||
Table A.11 shows the AXI read address channel signals.
Table A.11. Read address channel signals
| Signal | AMBA equivalent [a] |
|---|---|
| araddr[31:0] | ARADDR |
| arburst[1:0] | ARBURST[1:0] |
| arcache[3:0] [b] | ARCACHE[3:0] |
| arid[AID_WIDTH-1:0] [c] | ARID |
| arlen[3:0] | ARLEN[3:0] |
| arlock[1:0] | ARLOCK[1:0] |
| arprot[2:0] [b] | ARPROT[2:0] |
| arready | ARREADY |
| arsize[2:0] | ARSIZE[2:0] |
| arvalid | ARVALID |
[a] See the AMBA AXI Protocol Specification for a description of these signals. [b] The DDR2 DMC ignores any information that it receives on these signals. [c] The value of AID_WIDTH is set during configuration of the DDR2 DMC. | |
| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
| PDF version | |
| Home > Signal Descriptions > AXI signals > Read address channel signals |