2.2.3. AXI low-power interface

The low-power interface can move the DDR2 DMC into its Low_power state without the requirement for any register accesses, see Figure 2.13 and Power-down support and usage model.

For more information about the AXI low-power interface, see the AMBA AXI Protocol Specification.

If you do not require the low-power interface, tie it off as the CoreLink DDR2 Dynamic Memory Controller (DMC-341) Integration Manual describes.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910