| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
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Table A.15 shows the legacy pad interface signals.
Table A.15. Legacy pad interface signals
| Signal | Type | Source or destination | Description | ||
|---|---|---|---|---|---|
| Signals for a DDR2 DMC, with or without ECC support: | |||||
| add[15:0] | Output | External memory | Address | ||
| ap | Output | External memory | Auto precharge | ||
| ba[MEMORY_BANK_WIDTH-1:0][a] | Output | External memory | Bank select | ||
| cas_n | Output | External memory | Column address strobe | ||
| cke | Output | External memory | Clock enable | ||
| clk_out[MEMORY_CHIPS-1:0][b] | Output | External memory | Memory clock | ||
| cs_n[MEMORY_CHIPS-1:0] | Output | External memory | Chip select | ||
| data_en | Output | External memory | Data direction enable | ||
| dqm[MEMORY_BYTES-1:0][c] | Output | External memory | Data bus mask | ||
| dqs_in_<n> | Input | External memory | Data strobe in | ||
| dqs_in_n_<n> | Input | External memory | Data strobe in bar | ||
| dqs_out_<n> | Output | External memory | Data strobe out | ||
| odt[MEMORY_CHIPS-1:0] | Output | External memory | Memory IO termination control | ||
| odt_read | Output | Output pad IO | Device IO termination control | ||
| ras_n | Output | External memory | Row address strobe | ||
| we_n | Output | External memory | Write enable | ||
| Signals for a DDR2 DMC without ECC support: | |||||
| dq_in[MEMWIDTH-1:0] [d] | Input | External memory | Data bus in | ||
| dq_out[MEMWIDTH-1:0] [d] | Output | External memory | Data bus out | ||
| Signals for a DDR2 DMC with ECC support: | |||||
| dq_in[MEMWIDTH+ECCWIDTH-1:0] [e] | Input | External memory | Data bus in | ||
| dq_out[MEMWIDTH+ECCWIDTH-1:0] [e] | Output | External memory | Data bus out | ||
| dqs_in_ecc | Input | External memory | ECC strobe in | ||
| dqs_in_n_ecc | Input | External memory | ECC strobe in bar | ||
| dqs_out_ecc | Output | External memory | ECC strobe out | ||
[a] The MEMORY_BANK_WIDTH value depends on the number of banks in the configuration. [b] MEMORY_CHIPS is the number of chip selects and is set during configuration of the DDR2 DMC. [c] MEMORY_BYTES is the width of the external memory data bus in bytes and is set during configuration of the DDR2 DMC. [d] MEMWIDTH is the width of the external memory data bus in bits and is set during configuration of the DDR2 DMC. [e] The value of ECCWIDTH depends on MEMWIDTH as follows: - if MEMWIDTH = 16 then ECCWIDTH = 6 - if MEMWIDTH = 32 then ECCWIDTH = 7 - if MEMWIDTH = 64 then ECCWIDTH = 8. | |||||
| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
| PDF version | |
| Home > Signal Descriptions > Pad interface signals > Legacy pad interface |