A.3.1. Write address channel signals

Table A.8 shows the AXI write address channel signals.

Table A.8. Write address channel signals

Signal AMBA equivalent [a]
awaddr[31:0]AWADDR
awburst[1:0]AWBURST[1:0]
awcache[3:0] [b]AWCACHE[3:0]
awid[AID_WIDTH-1:0] [c]AWID
awlen[3:0]AWLEN[3:0]
awlock[1:0]AWLOCK[1:0]
awprot[2:0] [b]AWPROT[2:0]
awreadyAWREADY
awsize[2:0]AWSIZE[2:0]
awvalidAWVALID

[a] See the AMBA AXI Protocol Specification for a description of these signals.

[b] The DDR2 DMC ignores any information that it receives on these signals.

[c] The value of AID_WIDTH is set during configuration of the DDR2 DMC.


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