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Table A.9 shows the AXI write data channel signals.
Table A.9. Write data channel signals
| Signal | AMBA equivalent [a] |
|---|---|
| wdata[AXI_DATA_MSB:0] [b] | WDATA |
| wid[AID_WIDTH-1:0] [b] | WID |
| wlast | WLAST |
| wready | WREADY |
| wstrb[AXI_STRB_MSB:0] [b] | WSTRB |
| wvalid | WVALID |
[a] See the AMBA AXI Protocol Specification for a description of these signals. [b] The value of AXI_DATA_MSB and AID_WIDTH are set during configuration of the DDR2 DMC. AXI_STRB_MSB = AXI_DATA_MSB ÷ 8. | |
| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
| PDF version | |
| Home > Signal Descriptions > AXI signals > Write data channel signals |