CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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A.3.3. Write response channel signals

Table A.10 shows the AXI write response channel signals.

Table A.10. Write response channel signals

Signal AMBA equivalent [a]
bid[AID_WIDTH-1:0] [b]BID
breadyBREADY
bresp[1:0] [c]BRESP[1:0]
bvalidBVALID

[a] See the AMBA AXI Protocol Specification for a description of these signals.

[b] The value of AID_WIDTH is set during configuration of the DDR2 DMC.

[c] The DDR2 DMC ties bresp[1] LOW and therefore it only provides OKAY or EXOKAY responses.


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