^[a] See the AMBA AXI Protocol Specification for a description of these signals.

^[b] The value of AXI_DATA_MSB and AID_WIDTH are set during configuration of the DDR2 DMC.

^[c] It is possible for refreshes to be missed if rready is held LOW for longer than one refresh period, and the read data FIFO, command FIFO, and arbiter queue become full. An OVL error is triggered if this occurs in simulation. Ensure that the device has a sufficiently high system priority to prevent this.

^[d] The DDR2 DMC ties rresp[1] LOW and therefore it only provides OKAY or EXOKAY responses.