A.2.2. Tie-offs

Table A.3 shows the tie-off signals.

Table A.3. Tie-off signals

SignalTypeSourceDescription
bank_bits[1:0]InputTie-offWhen aresetn is deasserted, the state of this signal sets the value of the bank_bits field in the memory_cfg2 Register. See Memory Configuration 2 Register for information about the values that a configured controller permits.
cke_initInputTie-off

When aresetn is deasserted, the state of this signal sets the value of the cke_init bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

dqm_initInputTie-off

When aresetn is deasserted, the state of this signal sets the value of the dqm_init bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

This signal is only available when the DDR2 DMC is configured to provide a legacy pad interface.

memory_width[1:0]InputTie-offWhen aresetn is deasserted, the state of this signal sets the value of the memory_width2 field in the memory_cfg2 Register. See Memory Configuration 2 Register for information about the values that a configured controller permits.

sync

Input

Tie-off

When aresetn is deasserted, the state of this signal sets the value of the clock_cfg [0] bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

Set this signal HIGH if aclk is synchronous to mclk.

Set this signal LOW if aclk is asynchronous to mclk.


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