A.5.2. DFI pad interface

Table A.16 shows the DFI pad interface signals. See the DDR PHY Interface (DFI) Specification for a description of these signals.

Table A.16. DFI pad interface signals

  SignalTypeSource or destination
 Signals for a DDR2 DMC, with or without ECC support:
 dfi_address[15:0]OutputPHY device
 dfi_bank[MEMORY_BANK_WIDTH-1:0] [a]Output
 dfi_cas_nOutput
 dfi_cke[MEMORY_CHIPS-1:0] [b]Output
 dfi_cs_n[MEMORY_CHIPS-1:0] [b]Output
 dfi_dram_clk_disable[MEMORY_CHIPS-1:0] [b]Output
 dfi_init_completeInput
 dfi_odt[MEMORY_CHIPS-1:0] [b]Output
 dfi_phyupd_ackOutput
 dfi_phyupd_reqInput
 dfi_phyupd_type[1:0]Input
 dfi_ras_nOutput
 dfi_we_nOutput
 Signals for a DDR2 DMC without ECC support: 
 dfi_rddata[2×MEMWIDTH-1:0] [c]InputPHY device
 dfi_rddata_en[2×MEMORY_BYTES-1:0] [d]Output
 dfi_wrdata_en[2×MEMORY_BYTES-1:0] [d]Output
 dfi_wrdata[2×MEMWIDTH-1:0] [c]Output
 dfi_wrdata_mask[2×MEMORY_BYTES-1:0] [d]Output
 Signals for a DDR2 DMC with ECC support:
 dfi_rddata[2×(MEMWIDTH+ECCWIDTH)-1:0] [c] [e]InputPHY device
 dfi_rddata_en[2×(MEMORY_BYTES+1)-1:0] [d]Output
 dfi_wrdata_en[2×(MEMORY_BYTES+1)-1:0] [d]Output
 dfi_wrdata[2×(MEMWIDTH+ECCWIDTH)-1:0] [c] [e]Output
 dfi_wrdata_mask[2×(MEMORY_BYTES+1)-1:0] [d]Output

[a] The MEMORY_BANK_WIDTH value depends on the number of banks in the configuration.

[b] MEMORY_CHIPS is the number of chip selects and is set during configuration of the DDR2 DMC.

[c] MEMWIDTH is the width of the external memory data bus in bits and is set during configuration of the DDR2 DMC.

[d] MEMORY_BYTES is the width of the external memory data bus in bytes and is set during configuration of the DDR2 DMC.

[e] The value of ECCWIDTH depends on MEMWIDTH as follows:

      -  if MEMWIDTH = 16 then ECCWIDTH = 6

      -  if MEMWIDTH = 32 then ECCWIDTH = 7

      -  if MEMWIDTH = 64 then ECCWIDTH = 8.


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