A.2.5. Interrupt signals

Table A.6 shows the ECC interrupt signals when a DDR2 DMC is configured to support ECC.

Table A.6. ECC interrupt signals

ecc_ded_intOutputInterrupt controllerECC double-error detect signal. If the DDR2 DMC detects a non-correctable double-error then is sets this signal HIGH.
ecc_overflow_intOutputInterrupt controllerECC overflow signal. If the DDR2 DMC attempts to set ecc_ded_int or ecc_sec_int HIGH but that signal is already HIGH then it sets this overflow signal HIGH.
ecc_sec_intOutputInterrupt controllerECC single-error correct signal. If the DDR2 DMC corrects a single bit-error then is sets this signal HIGH.

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