CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.14. ACTIVE to ACTIVE Different Bank Timing Register

The t_rrd Register characteristics are:

Purpose

Controls the ACTIVE bank x to ACTIVE bank y delay in memory clock cycles, see Figure 2.18.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.21 shows the t_rrd Register bit assignments.

Figure 3.21. t_rrd Register bit assignments

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Table 3.15 shows the t_rrd Register bit assignments.

Table 3.15. t_rrd Register bit assignments

BitsNameFunction
[31:4]-Read undefined, write as zero.
[3:0]t_rrdSets tRRD, the ACTIVE bank x to ACTIVE bank y delay in memory clock cycles. Supported values are 1-15.

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