3.3.16. Write to Read Timing Register

The t_wtr Register characteristics are:


Controls the Write to Read delay in memory clock cycles, see Figure 2.24.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.23 shows the t_wtr Register bit assignments.

Figure 3.23. t_wtr Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.17 shows the t_wtr Register bit assignments.

Table 3.17. t_wtr Register bit assignments

[31:3]-Read undefined, write as zero.
[2:0]t_wtrSets tWTR, the Write to Read command delay in memory clock cycles. Supported values are 1-7.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E