3.3.2. Memory Controller Command Register

The memc_cmd Register characteristics are:


Controls the operating state of the DDR2 DMC.

Usage constraints

Not accessible in the Reset or Power On Reset (POR) state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.9 shows the memc_cmd Register bit assignments.

Figure 3.9. memc_cmd Register bit assignments

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Table 3.3 shows the memc_cmd Register bit assignments.

Table 3.3. memc_cmd Register bit assignments

[31:3]-Undefined, write as zero.



Use the following commands to change the state of the DDR2 DMC:

0b000 = Go

0b001 = Sleep

0b010 = Wakeup

0b011 = Pause

0b100 = Configure

0b111 = Active_Pause.

If the controller receives a command to change state and a previous command to change state has not completed then it holds pready LOW until the new command can be carried out.

See Figure 2.13 for more information about the state transitions.


  • Active_Pause command puts the DDR2 DMC into the Paused state without draining the arbiter queue. This enables you to move the controller to the Low_power state, to change configuration settings such as memory frequency or timing register values, without requiring co-ordination between masters in a multi-master system.

  • If you use the Active_Pause command to put the controller in the Low_power state then you must not remove power from the controller because this results in data loss and violation of the AXI protocol.

  • The controller does not issue refreshes when in the Config state. Therefore, ARM recommends that you make register updates with the controller in Low_power state because this ensures that the memory is put into self-refresh mode, rather than the Config state when the memory contains valid data.

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