3.3.13. PRECHARGE to Command Timing Register

The t_rp Register characteristics are:

Purpose

Controls the PRECHARGE to RAS delay in memory clock cycles, see Figure 2.19 and Figure 2.20.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.20 shows the t_rp Register bit assignments.

Figure 3.20. t_rp Register bit assignments

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Table 3.14 shows the t_rp Register bit assignments.

Table 3.14. t_rp Register bit assignments

BitsNameFunction
[31:11]-Read undefined, write as zero.
[10:8]schedule_rpSets the PRECHARGE to RAS delay in aclk clock cycles minus 3. It is used as a scheduler delay and values in the range 0-4 are supported.
[7:4]-Read undefined, write as zero.
[3:0]t_rpSets tRP, the PRECHARGE to RAS delay in memory clock cycles. Supported values are 1-7.

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