3.3.15. Write to PRECHARGE Timing Register

The t_wr Register characteristics are:

Purpose

Controls the Write to PRECHARGE delay in memory clock cycles, see Figure 2.25.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.22 shows the t_wr Register bit assignments.

Figure 3.22. t_wr Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.16 shows the t_wr Register bit assignments.

Table 3.16. t_wr Register bit assignments

BitsNameFunction
[31:3]-Read undefined, write as zero.
[2:0]t_wrSets tWR, the Write to PRECHARGE delay in memory clock cycles. Supported values are 2-6.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910