CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 3.3.3. Direct Command Register

3.3.3. Direct Command Register

The direct_cmd Register characteristics are:

Purpose

Initializes and updates the external memory devices by sending the following commands:

NOP
PRECHARGEALL
AUTO REFRESH
MODEREG.

Usage constraints

Only accessible in Config state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

The direct_cmd Register therefore enables any initialization sequence that an external memory device might require. The only timing information associated with the direct_cmd Register are the command delays that are programmed in the timing registers. Figure 3.2 shows the timing registers. Therefore, if an initialization sequence requires additional delays between commands, they must be timed by the master driving the initialization sequence.

Figure 3.10 shows the direct_cmd Register bit assignments.

Figure 3.10. direct_cmd Register bit assignments

Table 3.4 shows the direct_cmd Register bit assignments.

Table 3.4. direct_cmd Register bit assignments

Bits	Name	Function
[31:22]	-	Undefined, write as zero.
[21:20]	chip_addr	Bits mapped to external memory chip selects, cs_n[MEMORY_CHIPS-1:0] or dfi_cs_n[MEMORY_CHIPS-1:0].
[19:18]	memory_cmd	Selects the command required: `0b00` = PRECHARGEALL `0b01` = AUTO REFRESH `0b10` = MODEREG or Extended MODEREG access `0b11` = NOP.
[17:16]	bank_addr	Bits mapped to external memory bank address bits, ba[1:0] or dfi_bank[1:0], when the controller issues a MODEREG command.
[15:14]	-	Undefined, write as zero.
[13:0]	addr_13_to_0	Bits mapped to external memory address bits, add[13:0] or dfi_address[13:0], when the controller issues a MODEREG command.

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