CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.17. Exit Power-down Timing Register

The t_xp Register characteristics are:

Purpose

Controls the exit power-down to command delay in memory clock cycles, see Figure 2.23.

Usage constraints

Only accessible in Config or Low_power state.

You must only write when either:

  • auto_power_down bit is 0, see Table 3.5

  • DDR2 DMC is in the Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.24 shows the t_xp Register bit assignments.

Figure 3.24. t_xp Register bit assignments

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Table 3.18 shows the t_xp Register bit assignments.

Table 3.18. t_xp Register bit assignments

BitsNameFunction
[31:8]-Read undefined, write as zero.
[7:0]t_xpSets tXP, the exit power-down to command delay in memory clock cycles. Supported values are 1-255.

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