CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.11. ACTIVE to Read or Write Timing Register

The t_rcd Register characteristics are:

Purpose

Controls the RAS to CAS minimum delay in memory clock cycles and controls the delay between an ACTIVE command and another memory command, other than ACTIVE, to the same bank, see Figure 2.15.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.18 shows the t_rcd Register bit assignments.

Figure 3.18. t_rcd Register bit assignments

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Table 3.12 shows the t_rcd Register bit assignments.

Table 3.12. t_rcd Register bit assignments

BitsNameFunction
[31:11]-Read undefined, write as zero.
[10:8]schedule_rcdSets the RAS to CAS minimum delay in aclk clock cycles minus 3. It is used as a scheduler delay and values in the range 0-4 are supported.
[7:3]-Read undefined, write as zero.
[2:0]t_rcdSets tRCD, the RAS to CAS minimum delay in memory clock cycles. Supported values are 1-7.

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