CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: A.1. Clock and reset signals

CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual

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A.1. Clock and reset signals

Table A.1 shows the clock and reset signals.

Table A.1. Clock and reset signals

Signal	Type	Source	Description
aclk	Input	Clock source	Clock for the aclk domain.
aresetn	Input	Reset source	aclk domain reset signal. This signal is active LOW.
cclken	Input	Bus clock	Clock enable for the AXI low-power interface.
mclk	Input	Clock source	Clock for mclk domain.
mclkn ^[a]	Input	Clock source	Optional clock for the legacy pad interface.
mclkx2 ^[a]	Input	Clock source	Optional clock for the legacy pad interface.
mclkx2n ^[a]	Input	Clock source	Optional clock for the legacy pad interface.
mresetn	Input	Reset source	Reset for mclk domain. This signal is active LOW.
pclken	Input	Bus clock	Clock enable for the APB interface.
^[a]This signal is not available when the DDR2 DMC is configured to implement a DDR PHY Interface (DFI) pad interface.

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