A.1. Clock and reset signals

Table A.1 shows the clock and reset signals.

Table A.1. Clock and reset signals

SignalTypeSourceDescription
aclkInputClock sourceClock for the aclk domain.
aresetnInputReset sourceaclk domain reset signal. This signal is active LOW.
cclkenInputBus clockClock enable for the AXI low-power interface.
mclkInputClock sourceClock for mclk domain.
mclkn [a]InputClock sourceOptional clock for the legacy pad interface.
mclkx2 [a]InputClock sourceOptional clock for the legacy pad interface.
mclkx2n [a]InputClock sourceOptional clock for the legacy pad interface.
mresetnInputReset sourceReset for mclk domain. This signal is active LOW.
pclkenInputBus clockClock enable for the APB interface.

[a] This signal is not available when the DDR2 DMC is configured to implement a DDR PHY Interface (DFI) pad interface.


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