1.1.2. Supported memory widths

The read data FIFO and write data buffer widths are equal to the greater of the AXI or the effective memory data width.

Table 1.1 shows the supported combinations of memory and AXI bus widths.

Table 1.1. Supported combinations of memory and AXI data widths

CombinationMemory data widthEffective memory data width[a]AXI data width
a16-bit  32-bit  32-bit
b16-bit  32-bit  64-bit
c32-bit  64-bit  32-bit
d32-bit  64-bit  64-bit
e32-bit  64-bit128-bit
f64-bit128-bit  64-bit
g64-bit128-bit 128-bit

[a] Effective memory data width is equal to the size of transfer on a per-cycle basis on the memory interface.


  • In addition to the choice of memory data widths at render time, you can modify the DDR2 DMC to use half the configured memory width by either:

  • When modifying the configured memory width you must ensure that the:

    • new memory width is not less than 16 bits

    • effective memory width is not less than half the AXI slave interface data width.

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