CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 1.1.2. Supported memory widths

The read data FIFO and write data buffer widths are equal to the greater of the AXI or the effective memory data width.

Table 1.1 shows the supported combinations of memory and AXI bus widths.

Table 1.1. Supported combinations of memory and AXI data widths

Combination	Memory data width	Effective memory data width^[a]	AXI data width
a	16-bit	32-bit	32-bit
b	16-bit	32-bit	64-bit
c	32-bit	64-bit	32-bit
d	32-bit	64-bit	64-bit
e	32-bit	64-bit	128-bit
f	64-bit	128-bit	64-bit
g	64-bit	128-bit	128-bit
^[a]Effective memory data width is equal to the size of transfer on a per-cycle basis on the memory interface.

In addition to the choice of memory data widths at render time, you can modify the DDR2 DMC to use half the configured memory width by either:
- using the memory_width[1:0] tie-off signals
- programming the memory_width2 field in the Memory Configuration 2 Register.
When modifying the configured memory width you must ensure that the:
- new memory width is not less than 16 bits
- effective memory width is not less than half the AXI slave interface data width.

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