3.3.6. CAS Latency Register

The cas_latency Register characteristics are:


Controls the CAS latency time in memory clock cycles, see Figure 2.26.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.13 shows the cas_latency Register bit assignments.

Figure 3.13. cas_latency Register bit assignments

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Table 3.7 shows the cas_latency Register bit assignments.

Table 3.7. cas_latency Register bit assignments

[31:4]-Read undefined, write as zero.
[3:1]cas_latencyCAS latency in mclk cycles. Supported values are 3-6.
[0]-Undefined, read and write as zero.

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