CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.10. ACTIVE to ACTIVE Timing Register

The t_rc Register characteristics are:

Purpose

Controls the ACTIVE bank x to ACTIVE bank x delay in memory clock cycles, see Figure 2.17.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.17 shows the t_rc Register bit assignments.

Figure 3.17. t_rc Register bit assignments

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Table 3.11 shows the t_rc Register bit assignments.

Table 3.11. t_rc Register bit assignments

BitsNameFunction
[31:5]-Read undefined, write as zero.
[4:0]t_rcSets tRC, the ACTIVE bank x to ACTIVE bank x delay in memory clock cycles. Supported values are 1-31.

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